The present invention relates to a semiconductor device and a manufacturing technology thereof, in particular, to a nonvolatile semiconductor memory device having, over one semiconductor substrate thereof, both a binary memory cell and a multivalued memory cell and a technology effective when applied to the manufacture of the device.
Japanese Patent Laid-Open No. 2003-22687 describes a technology of improving the reliability of a nonvolatile semiconductor memory device and reducing an area occupied by a memory array. More specifically, according to this technology, an address region of a binary mode memory cell in which one memory cell stores one bit of data and an address region of a multivalued memory cell in which one memory cell stores multiple bits of data are fixed, respectively. Fixing of the address regions in such a manner makes it possible to optimize the binary memory cell and the multivalued memory individually.
Japanese Patent Laid-Open No. Hei 11 (1999)-31102 describes a technology of having a binary memory and a multivalued memory on one substrate. It also describes a technology of controlling this semiconductor device having a plurality of memories, that is, a binary memory and a multivalued memory to select the optimum one from them, depending on data accessed by a host system.
Japanese Patent Laid-Open No. 2006-260703 describes a nonvolatile semiconductor memory device facilitating realization of a multivalued memory while preventing control of a threshold voltage and a read-out circuit from becoming complicated. In this nonvolatile semiconductor memory device, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode.